Yes, my statement was not about the quality or performance of the chip -- simply the tapeout timeline that was stated, by itself.

i don't understand what the second paragraph is saying.

I don't think you get the newcomer novelty buff when your val approaches 13 digits.

The typical way a chip effort in a non-chip company works is that the "design" is the RTL (e.g. SystemVerilog that defines the behavior of the chip) and then this is handed off to a third-party "design house" (such as Broadcom) that turns that code into a real image of a chip, which is called a GDS (basically you can think of this as a very big layer by layer photoshop file) that can actually be sent to a fab. This is called "backend design", in contrast to the "frontend design" (the RTL itself).

As another commenter said, Broadcom is very experienced with backend design (as well as the supply chain management, testing, etc. that comes after the chip is taped out) and so this can't be regarded as a "first chip". Richard Ho (the head of hardware at OpenAI) is also extremely experienced and used to be the head of the Google TPU effort -- where he actually worked with Broadcom in a similar tapeout already. So yes, this is not a "first design"!

This isn't Broadcom's first design.

> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing.

PCB design and 3D CAD design are different topics.

Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog

PCB layout is an art, and doesn't seem to map well to LLMs (I tried for shits and giggles recently). Claude in general, kind of like code, does a lot of redundant belt and suspenders stuff in the schematics it generates (if it can generate them at all). It's one of those things that's really not there yet outside of the simplest designs.

Does it work better when using compiler based ecosystem (e.g. https://github.com/llvm/circt)

There is quite a lot of Verilog/SystemVerilog and VHDL code in the wild. And hardware description language code is very simple and straightforward relative to programming code.

And the two things that take up VAST amounts of time in ASIC design are testbenches and timing closure.

A LOT of hardware design is testbenches to verify things. AI is REALLY GOOD at generating things like testbenches. And nobody really cares if the quality of your testbench code sucks as long as it validates what it claims to.

I don't know how good AI is at timing closure, but I wouldn't necessarily be surprised if it is pretty good at it up to the physical point. That's lots of textual output which you can put a constraint on.

Everything involving physical design, though, tends to be a disaster waiting to happen if you let AI loose on it.

hasn't pcbway been doing this for years?

Doesn’t Broadcom bring a lot more to bear here than just Verilog? Including relationships with the actual fabricators.

Not having a free toolchain that can actually handle the real language has probably been pretty bad on the downstream public knowledgebase. Hopefully Verilator can eventually close that hole, and there can be more high-quality designs and codebases incorporated into future models. Claude is at least good enough to write SV that triggered a compiler crash or two. :)

They have. That's why OpenAI was able to get a working demo in 9 months. But going from a small scale system to a full fledged data center deployment is likely much harder.

I don't know how much of the things outside of the chip Broadcom has vs Google's proprietary tech that is not shared with Broadcom.

Nvidia's Vera Rubin has 6 unique chips working together in a single rack.[0]

[0]https://developer-blogs.nvidia.com/wp-content/uploads/2026/0...

at the hardware company I work at, people are now using claude code and developing skills for it to do basic stuff like triage or do initial debug on failing tests, search for potential causes in RTL, generate skeleton documentation for designs etc

I'd be shocked if it was anything more than this.

From time to time? Lol you must realize, frontier lab eng are using Codex/Claude-Code 99% in loops, on models the public doesn't have access to. Why? Because it works. Just a matter of time before humans are out of the loop and what comes next is a black hole

"The future is here, it's just not evenly distributed"

Yes, obviously. But do we think LLMs without access to proprietary information do a better job with them than Broadcom's human experts or existing proprietary tools at this level of operations?

It is still a bold claim and it still needs evidence.

We would obviously get a bit more of the evidence if it were to be more useful for the upcoming IPO than this rather open-ended, reinterpretable phrasing.

I don't understand why you're getting downvoted.

I've used GPT-5.5 and Opus both for FPGA design with good results. We built a lot of tooling around it to help the models, but even without that they're definitely capable of designing digital logic.

> solve our hardest math problems

We're not quite there yet :)

https://en.wikipedia.org/wiki/List_of_unsolved_problems_in_m...

> Why is that a bold and unlikely claim?

Because they could have offered even slightly more evidence.

Because then they'd likely have stfu and outperformed Intel, Nvidia and AMD, or at least one of them.

They're burning more cash than pretty much anyone else and doesn't have anything public that looks like a matching revenue stream so they probably need one very badly.

[dead]

novel to whom, the reader or the industry?

something can be non-novel in the industry, yet novel to the reader, at which point it is useful ... for such readers.