| ▲ | whynotminot 7 hours ago |
| Big deal, smart for all parties, really. Apple standards will make Intel step up and become a better foundry partner. Apple will gain increasingly needed diversification. US supply chain gets a boost. Should be fine for TSMC in the short to medium term. Apple not going to risk actual mainline iPhone SoC on Intel any time soon, so lion share of TSMC Apple revenue will be fine. |
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| ▲ | aurareturn 6 hours ago | parent | next [-] |
| The biggest reason to do this is because TSMC's N2 node and future nodes will be dominated by AI chips. Since AI chips have far bigger margins than most Apple chips, Apple will get outbid by companies like Nvidia, AMD, and Broadcom. Nvidia already became TSMC's biggest customer last year. Every TSMC advanced node from N5 to N2 is fully booked and running at max capacity. It's not really realistic to make Mac, Watch, iPad chips on TSMC's best node in the next 3-4 years - assuming there is no collapse in AI. Unfortunately, this might mean we will get inferior Intel chips for our Macs. Intel nodes, as it stands, are far more power hungry, less dense, and lower yielding. Intel's own Panther Lake CPU tile is on 18A and it's extremely disappointing in terms of perf/watt and raw perf. I still expect iPhone chips to be made on the best TSMC nodes though. I'm assuming Apple will design every future core for both TSMC and Intel, sort of like how they dual sourced with TSMC and Samsung in the past for the same generation. |
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| ▲ | adrian_b 3 hours ago | parent | next [-] | | I do not know on what data you base your sentence "Intel's own Panther Lake CPU tile is on 18A and it's extremely disappointing in terms of perf/watt and raw perf." Panther Lake does not have great raw performance, because for now Intel has not succeeded to obtain in their new 18A CMOS process clock frequencies as high as they get in the older TSMC 3-nm process used for their previous Arrow Lake H CPU generation and the CPU cores of Panther Lake have only minor changes that can affect performance in comparison with Arrow Lake/Lunar Lake. On the other hand, from the published reviews that I have seen, Panther Lake has significantly better performance per watt than Arrow Lake H, which can be attributed only to the Intel 18A process when compared with the TSMC 3 nm process. The energy efficiency i.e. performance per watt ratio of CPUs is mainly determined by the fabrication process and not by the CPU design, as long as the CPU designers are competent enough (unlike the single-thread performance, which is determined mainly by the CPU design). So there is no doubt that Apple CPUs made with the Intel 18A process will have better performance per watt than those made with a TSMC 3-nm process. Moreover, because Apple CPUs can reach a given level of performance at lower clock frequencies, they should be much less affected by the lower clock frequencies attainable with Intel 18A than the Intel CPUs. We also do not know whether Apple intends to use the Intel 18A process (currently used for Panther Lake laptop CPUs and Clearwater Forest server CPUs), or only its successor, Intel 14A. | | |
| ▲ | aurareturn 3 hours ago | parent [-] | | All efficiency data can be found here: https://www.notebookcheck.net/Intel-Panther-Lake-Core-Ultra-... The most important one for efficiency is ST perf/watt. MT perf/watt is largely based on how many cores there are. You can achieve better MT perf/watt simply by having more cores (more transistors) and run them at lower clocks. Panther Lake also has an entirely new MT config with 3 tiers of cores vs 2 for Arrow Lake. For ST perf/watt, it loses to LNL. Keep in mind that LNL and Arrow Lake used N3B, and future N3 nodes have been much more efficient. Panther Lake CPU is also a new design which should have improved perf/watt automatically regardless of node. Based on this, one can deduce that Intel 18A is likely a bit worse than N3B and perhaps equivalent to N4P. Keep in mind that N3B went into production in late 2022 and N4P was a 2021 node. |
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| ▲ | brookst 5 hours ago | parent | prev | next [-] | | Nvidia’s chips aren’t usually on the latest nodes. The M5 is in N3P, Blackwell is N4P. M6 is expected to be on an N2 node while Rubin is N3P. I don’t think Nvidia even has an N2 chip announced, could be wrong through. | | |
| ▲ | aurareturn 5 hours ago | parent [-] | | Nvidia’s chips aren’t usually on the latest nodes.
Not yet. The primary reason is because most AI chips are full reticle sized which means the first year yields likely won't be very cost effective. It takes a new node a few years to fully mature in terms of yield. Little iPhone A series and server CPU chiplets are perfect for new nodes.That said, Nvidia will certainly try to move smaller and lower volume chips in future generations to the most cutting edge node such as their CPUs, networking chips. Vera Rubin has 7 unique chips. They don't need be all on the same node, and they're not. AMD is taking up much of the N2 supply with their Epyc CPUs this year. There is no doubt in my mind that Nvidia, ARM, Graviton will try to book as much of the most cutting edge node as possible for their future enterprise CPUs given that AMD has done it for N2. I can see enterprise CPUs becoming equal launch partners to TSMC nodes as Apple. Agentic AI is going to cause a huge demand increase in CPUs. |
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| ▲ | zitterbewegung 5 hours ago | parent | prev | next [-] | | Apple arguably are making AI workstations that can do inference and training by their Mac Studio and Macbook Pros to a lesser extent. The M6 generation is going to be interesting and before the memory pricing going up their products were competitive to the rest of the industry. Intel is still working with small and smaller process nodes. | | |
| ▲ | aurareturn 5 hours ago | parent [-] | | Yes, I want Apple to focus on Mac inference. It could be the return of laptops/desktops as a major revenue source for Apple. Macs have been ~10% of Apple's revenue for the last 10 years or so. I'd love to see Macs get up to 20-30%. I do expect personal AI machines to take off in a few years once local models and local hardware hit an inflection point. M5 Max is a major improvement for local inference due to the added matmul accelerators, but the RAM capacity and bandwidth bottleneck is huge. That said, enterprise AI chips will still take the cake in terms of margins. | | |
| ▲ | bigyabai 2 hours ago | parent [-] | | At any point in the last six years, Apple could have signed Nvidia's aarch64 BSD drivers and watched their revenue climb. It's a minuscule commitment that is fully supported by the higher-end Mac Pros, only disabled by software. That would have sent sales skyrocketing as far as the supply could handle it. But Apple is about B2C, and customers buy services. All of us know, deep down, that Apple Intelligence will be a subscription service offered as part of Apple One. The Mac won't become the magical backbone for your personal inference network, it's a product used to consume Apple Services first and everything else comes second. |
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| ▲ | GeekyBear 5 hours ago | parent | prev | next [-] | | > TSMC's N2 node and future nodes will be dominated by AI chips. Apple was reported to have locked up half of the initial year's 2nm production, which is lower than their share of 3nm, but hardly a sign of being squeezed out of the market | | |
| ▲ | aurareturn 5 hours ago | parent [-] | | But this was likely locked up years ago before this boom. Will Apple still be the premier customer for TSMC's next node A14? Apple was actually told by TSMC to move off of N3 asap because Nvidia with its Vera Rubin and Google TPUs will take over. Semianalysis had a great and detailed article about TSMC & Apple and how the future might play out: https://newsletter.semianalysis.com/p/apple-tsmc-the-partner... | | |
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| ▲ | tobz1000 4 hours ago | parent | prev | next [-] | | Panther Lake's efficiency doesn't match M5, but it seems to be very good by all accounts. "Extremely disappointing" is a misrepresentation. | | |
| ▲ | aurareturn 4 hours ago | parent [-] | | Scroll to the "Cinebench 2024 Single Power Efficiency" section.[0] It doesn't even beat Lunar Lake in efficiency (made on TSMC N3B) released in 2024. [0]https://www.notebookcheck.net/Intel-Panther-Lake-Core-Ultra-... | | |
| ▲ | adrian_b 3 hours ago | parent | next [-] | | Besides the fact that Lunar Lake has a lower consumption in the memory interface, which has nothing to do with the fabrication process, single-thread benchmarks cannot be used to compare CPU fabrication processes. Both the absolute performance and the performance per watt in single-thread benchmarks are determined mainly by the CPU design and they are only slightly constrained by the CPU fabrication process. Only the multithreaded benchmarks are useful for comparing CMOS fabrication processes, because the performance in multithreaded benchmarks (with a given cooling system) is limited mainly by the energy required to switch a logic gate, which is a characteristic of the fabrication process, and they are only weakly dependent on the CPU design, as long as the CPU design does not have obvious mistakes. In multithreaded benchmarks, CPUs work at a fixed power consumption, determined by the maximum allowable temperature and the cooling system. A fixed power means a fixed number of gates that switch per second. The completion of a given benchmark requires a similar number of gate switchings in well designed CPUs, in which case the performance in such a benchmark is fully determined by the fabrication process. Deviations from proportionality appear when some CPUs need much less gate switchings than others to complete some work, which happens for example when a CPU has wider vector or matrix execution units, e.g. by supporting AVX-512 or SME or AMX. | | |
| ▲ | aurareturn 2 hours ago | parent [-] | | On package memory disproportionally affects idle power consumption more than load. In Cinebench 2024, which is a heavy load test, on package memory likely makes little difference. ST is far better than MT for this node comparison. MT is heavily influenced by core count, clock speed, core configuration. Panther Lake also has 3 tiers of cores compared to Arrow Lake's 2. The architecture for MT is entirely different. Meanwhile, for ST, a core is a core. It's less or not affected by architectural changes to core configurations. |
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| ▲ | williadc 4 hours ago | parent | prev [-] | | From the article you linked: > With the new Panther Lake mobile processors, Intel has managed to successfully combine the two previous generations, Arrow Lake and Lunar Lake, as the performance is even better than with Arrow Lake, while efficiency has been improved at the same time. Even with low power limits, the performance is very competitive, and Intel (in conjunction with the new GPUs) is therefore the better choice for slim laptops. | | |
| ▲ | aurareturn 4 hours ago | parent [-] | | Notice how it doesn't say it's more efficient than Lunar Lake. Their benchmarks say LNL is more efficient. | | |
| ▲ | adrian_b 3 hours ago | parent [-] | | The performance with LNL is not apples-to-apples, like the comparison with Arrow Lake H. LNL has a much lower power consumption in the memory interface, like the Apple CPUs, which has nothing to do with the fabrication process. Also LNL is a lower performance CPU, for which it is normal to have better energy efficiency. Only the comparison between Panther Lake and Arrow Lake H, which have equivalent structures, can be used to compare the Intel 18A and the TSMC 3-nm fabrication processes. This comparison shows that Intel 18A ensures a better performance per watt, i.e. energy efficiency, which leads to a better multithreaded performance, but the TSMC 3-nm process, at least for now, allows higher maximum clock frequencies, which make possible a higher single-thread performance. | | |
| ▲ | aurareturn 3 hours ago | parent [-] | | On-package memory disproportionately affect idle power more than load power. The benchmark was done with Cinebench 2024 which is a heavy load test. Therefore, LNL's on package memory would have made little to no difference overall to perf/watt in Cinebench 2024 ST. Only the comparison between Panther Lake and Arrow Lake H, which have equivalent structures, can be used to compare the Intel 18A and the TSMC 3-nm fabrication processes.
Panther Lake uses a new core design which likely contributed to better perf/watt regardless of which node was used. For example, Zen3 had a 19% increase in IPC despite being on the same N7 family node as Zen2. Panther Lake has 3 tiers of cores instead of 2 in Arrow Lake. The MT design is very different. New core and layout designs can make a huge difference in efficiency on the same node. This comparison shows that Intel 18A ensures a better performance per watt, i.e. energy efficiency, which leads to a better multithreaded performance, but the TSMC 3-nm process, at least for now, allows higher maximum clock frequencies, which make possible a higher single-thread performance.
We should compare ST perf/watt instead of MT. MT has too many factors including core count, die size, transistor count, clock speed.Based on ST perf/watt, Intel 18A is likely a bit worse than N3B (2022 node) and a bit better than N4P (2021 node). | | |
| ▲ | adrian_b 2 hours ago | parent [-] | | Panther Lake does not have new CPU cores. The Panther Lake cores, i.e. Darkmont and Cougar Cove are the Arrow Lake/Lunar Lake cores, i.e. Skymont and Lion Cove, ported from the TSMC 3 nm to the Intel 18A fabrication process. The Panther Lake cores have only minor changes, i.e. bug fixes and the addition of a new mechanism for interrupts and exceptions, FRED. A preliminary version of FRED is likely to have already been implemented on Arrow Lake/Lunar Lake, but if so it was disabled there after production. In any case FRED will not cause improvements in the present benchmarks, as it is used only inside the operating system and the current operating systems are unlikely to have been updated to use it anyway. In contradiction with what you say, ST performance or performance per watt cannot be used to compare fabrication processes but only the multithreaded performance can bu used for this purpose. Single-thread performance is affected by a lot of factors that have nothing to do with the fabrication process, but all those have little or no influence on multithreaded performance. The reason is that in any well optimized MT workload, the CPU runs at a constant power consumption. This eliminates the influence of all factors mentioned by you. I have already explained in another comment that a constant power consumption means a constant number of gate switchings per second, which is determined by the energy required to switch a logical gate, which is a characteristic of a fabrication process. When a given amount of work is done by a benchmark using the same algorithm, well-designed CPUs will need approximately the same number of gate switchings to complete the work, regardless of the number of cores included in a CPU. Significant variations of the numbers of gate switchings can be caused only by architectural differences like the width of vector and matrix execution units. Smaller variations are caused by various quality characteristics of a CPU core design, like the frequencies of branch mispredictions and of cache misses, which should be similar for CPU design teams that do not differ much in competence. When we compare equivalent cores in different fabrication processes, like Arrow Lake H vs. Panther Lake, the multithreaded benchmarks are almost unaffected by anything else except the fabrication process, assuming that the cooling systems are also equivalent. |
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| ▲ | 3 hours ago | parent | prev | next [-] | | [deleted] | |
| ▲ | LoganDark 5 hours ago | parent | prev [-] | | I find it ironic that Apple did the whole silicon thing to get away from Intel and now they are reportedly crawling back to Intel? I hope M6 and beyond continue to be competitive for inference. | | |
| ▲ | SoKamil 5 hours ago | parent | next [-] | | This is about FABs and not chip designs. Imagine a parallel universe where Apple was sourcing AMD chips (they actually did for graphic cards) and then went to TSMC to whom AMD is also a customer. Intel is both at the same time, AMD and TSMC. | | |
| ▲ | LoganDark 4 hours ago | parent [-] | | Note that I said M6 and beyond. I know the chip designs being produced will remain Apple's. Other commenters in the thread talk about how Intel's node is simply inferior to TSMC's and will bottleneck the performance of the same chip designs simply by being bad. I hope that is not the case and/or that I won't have to settle for an Intel node inside my Apple chips. (They better not try to pull an AMD where some chips simply have utterly kneecapped performance for no good reason.) |
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| ▲ | lostlogin 5 hours ago | parent | prev [-] | | That’s unlikely to be how it’s working out for Intel. Apple aren’t going to be asking for Intel Inside. It’ll be more like ‘Can you make this thing? How many and much?’ |
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| ▲ | 9cb14c1ec0 6 hours ago | parent | prev | next [-] |
| > Apple not going to risk actual mainline iPhone SoC on Intel any time soon Not to mention that Intel does not and will not any time in the next decade have the capacity for a product of that quantity. |
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| ▲ | aurareturn 5 hours ago | parent | next [-] | | ASML is one of the bigger bottlenecks I hear. They're fully booked out years in advance so even if Intel wants to build many more fabs, they can't. There was a recent interview with Dylan Patel and he explained it pretty well. Basically, there are tiers of risks and how "AGI pilled" each tier is. The bottlenecks and supply constraints get worse and worse as you down down the tiers. Tier 1: OpenAI/Anthropic - extremely AGI pilled and think it's a sure thing. They want all layers underneath to prepare to make as many chips as possible and go all in. Tier 2: Nvidia/AMD/Broadcom - very bullish but doesn't think AGI is a sure thing Tier 3: TSMC, Samsung, SK Hynix, Intel, Sandisk, Micron - bullish but if they're wrong and overbuild, they can actually go bankrupt. Each fab can cost tens of billions. An N2 fab is estimated to be $30b each. Tier 4: Every supplier to T3 such as ASML, Applied Materials, other fab machines and suppliers - Less bullish, may even see this as just a super cycle rather than a permanent increase in demand so they're less inclined to take too many risks to scale up | |
| ▲ | benced 5 hours ago | parent | prev [-] | | Next decade seems possibly false - if Intel starts getting deals and commitments now, it takes them about half a decade to build a fab. Agree it seems unlikely though. | | |
| ▲ | aurareturn 5 hours ago | parent [-] | | Intel doesn't even have enough capacity right now to make enough Xeon chips. CPU demand is absolutely booming but their Intel 18A and 3 nodes don't have great yields. |
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| ▲ | y3ahd0g 4 hours ago | parent | prev | next [-] |
| Time will tell but with Ternus taking over, a hardware and engineering mindset, could be going for a long term learn and build together, and of Intel can get it together and go where Apple needs, later buyout Intel. Lip-Bu Tan is a year older than Tim Cook. Doubt he wants to run Intel for very long. Would be hard for me in the Ternus role to not have that in mind if Intel gets it together. |
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| ▲ | twoodfin 4 hours ago | parent [-] | | I don’t imagine Apple views fab technology as a potential differentiator worth the massive investment. This is about diversifying their supply chain as they have done all over the place for decades. Displays, for example. | | |
| ▲ | y3ahd0g 3 hours ago | parent [-] | | That's why I wrote time will tell. The uncertainty of political order in the near term could make having fabs on their home turf as worth the security. Learn now, collaborate as preparation in case certain criteria politically, financially, are met. | | |
| ▲ | ua709 2 hours ago | parent [-] | | TSMC fabs on home turf is just as good from a security point of view. But in reality for VLSI at this scale and volume it’s just single supplier in series with single supplier all the way down. You don’t really get security with such a vulnerable supply chain, regardless of ownership. |
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| ▲ | signatoremo 6 hours ago | parent | prev | next [-] |
| It’s the main processor: Apple Inc. has held exploratory discussions about using Intel Corp. and Samsung Electronics Co. to produce the main processors for its devices in the US, a move that would offer a secondary option beyond longtime partner Taiwan Semiconductor Manufacturing Co. [0] (paywalled) They wouldn’t need either Intel or Samsung if it wasn’t bleeding edge. I think it’s 14A for Intel. TSMC is still have the edge overall, but they are neck and neck in terms of node. TSMC will be more than fine. They are hardly able to meet the demands. [0] https://www.bloomberg.com/news/articles/2026-05-05/apple-exp... |
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| ▲ | whynotminot 5 hours ago | parent [-] | | What does “main” mean? Main processor for a flagship iPhone? Or main processor for a HomePod? There’s a lot of “main” processors for Apple’s devices at this point. I would be deeply skeptical of a brand new flagship iPhone <n> Pro having an Intel fab’d SoC until at least a few years into this arrangement. | | |
| ▲ | ua709 2 hours ago | parent [-] | | Also an “exploratory discussion” is not the same as a signed contract. Apple has tons of custom silicon now. There are many low risk ASICs Apple could kick the tires with. |
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| ▲ | GeekyBear 6 hours ago | parent | prev | next [-] |
| This is the third year in a row that Apple's most advanced chips have used a version of TSMC's 3nm node, with a transition to a more advanced node due in the next generation. Intel would only need to be on par with TSMC's older 3nm node to Fab Apple's entry level SOCs. |
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| ▲ | Melatonic 5 hours ago | parent [-] | | Intel just bought a ton of ASML's most advanced machines (way more than TSMC) so theoretically they should be able to manufacture stuff on an equivalent node or better. And given the kind of performance and battery life we have seen from their latest chips they definitely seem to be back in the game | | |
| ▲ | aurareturn 4 hours ago | parent | next [-] | | Do you have a source of how many total EUV machines Intel bought and TSMC bought in the last 1-2 years? Yes, Intel made the first purchase for High NA EUV machines. That's largely because they were so far behind TSMC, they took a big risk as the first adopter for High NA EUV with their upcoming 14A node to try to catch up. TSMC thinks it can keep using low NA EUV machines for N2 and A14 nodes even if they have to increase the number of patterning steps. This also means TSMC will likely keep all the AI chip design wins since High NA has half of the reticle size of low NA. The maximum chip size of High NA is half of low NA. This is a major deal for AI chips because they tend to want to be as big as possible. None of these things mean Intel bought more total EUV machines than TSMC. A quick internet search says TSMC has about 2x as many fabs in active construction as Intel. | | |
| ▲ | GeekyBear 3 hours ago | parent [-] | | > TSMC thinks it can keep using low NA EUV machines for N2 and A14 nodes even if they have to increase the number of patterning steps. Intel thought they could skip buying into EUV at all and just increase their patterning steps. That didn't work out as well as they hoped. | | |
| ▲ | aurareturn 3 hours ago | parent [-] | | Actually, Intel tried to stuff too many advances into 10nm when ASML hasn't even shipped EUV machines yet. That's where they got stuck. Once they got stuck, EUV transitioned was delayed for Intel. |
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| ▲ | aurareturn 4 hours ago | parent | prev | next [-] | | And given the kind of performance and battery life we have seen from their latest chips they definitely seem to be back in the game
Panther Lake on 18A is less efficiency than Lunar Lake on N3B released in 2024.https://www.notebookcheck.net/Intel-Panther-Lake-Core-Ultra-... | |
| ▲ | ahartmetz 5 hours ago | parent | prev [-] | | "Big if true". That's surprising. More ASML machines = more capacity in the future. Do you have a source for that? Intel would need to have lots of (and / or very big) customers lined up or big plans to manufacture possibly more than CPUs of their own design to make use of that capacity. | | |
| ▲ | GeekyBear 5 hours ago | parent [-] | | They mention that Intel bought the initial production run in the page that introduced the new product. > can print transistors 1.7 times smaller – and therefore achieve transistor densities 2.9 times higher – than they can with NXE systems. https://www.asml.com/en/news/stories/2024/5-things-high-na-e... | | |
| ▲ | ahartmetz 3 hours ago | parent [-] | | Nothing about the number of machines in that article though. I could well see Intel buying the first ones of the new series as a PR coup. I mean obviously they are going to use them, too. | | |
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| ▲ | baq 5 hours ago | parent | prev [-] |
| > Apple standards Apple hardware standards. Apple software could use some of these. |
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| ▲ | carlosjobim 5 hours ago | parent [-] | | What does this have to do with the subject at hand? Is the internet like this now, that in every message board there is just islands of content floating in oceans of snark? | | |
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