> TSMC thinks it can keep using low NA EUV machines for N2 and A14 nodes even if they have to increase the number of patterning steps.

Intel thought they could skip buying into EUV at all and just increase their patterning steps.

That didn't work out as well as they hoped.

Actually, Intel tried to stuff too many advances into 10nm when ASML hasn't even shipped EUV machines yet. That's where they got stuck. Once they got stuck, EUV transitioned was delayed for Intel.