Sounds like innovator's dilemma to me. Their current production lines might be too profitable[0], so diverting expansion capacity to a yet unproven technology (to Micron's to-date profit margin requirements) might be too big of a financial hit. Since they're the ones who came up with 4F design, they must hold a ton of patents on the various incremental improvements. At which point, from a purely cynical and utilitarian view, it would make financial sense to let other players polish the remaining 20% and use patent portfolio as a wedge for mid-term technology transfers.

Or in short: "let others figure out the technical complexities and surrounding economics." - Which would make sense from a company that believes they can catch up once the expensive leg of the manufacturing/scaling research has been completed. Whether that bet is good or not, we'll see.

0: Didn't we read a few days ago here that all of 2027 production capacity has been sold out already?

> They have to explain what they are doing.

They really don't. A public company doesn't even have to provide forward-looking earnings guidance, though many choose to do so for strategic reasons. The only reason to make announcements is if there's some strategic benefit to doing so.

> that does not justify dropping the future innovation

Looks like they have mapped the possible paths and consider it a dead end. The density increase is low compared to the effort to process cost, so they just opted for a simpler process with a similar density at a much lower cost per wafer. They might come back to it at some point - they invented it and have substantial IP investment on it.

Also, there might be some cost of opportunity - the AI bubble is now, so anything that diverts from current extremely profitable product lines is a terrible idea. It’s a bubble and they have the fiduciary duty to suck it until it’s dry.

Those are completely misleading, because they are not the true cell layouts.

Searching for the Micron patent on 6F^2 cells (US 6,975,531) is much more informative.

The essence of the problem is the following. An ideal memory array cell is formed at the intersection of a vertical line with a horizontal line. A line has the width 2F (i.e. metal width + spacing width), so the area of the cell is 2F * 2F = 4F^2.

Instead of that, most DRAM cells are at the intersection of 2 horizontal lines with 1 vertical line. The single line is a bidirectional data line with the value of the stored bit, while the pair of lines are a write select line and a read select line.

Using separate read and write transistors provides better performance.

The naive layout for a cell where 2 lines intersect with 1 line has an area of 2F * 4F = 8F^2.

An optimized layout where many parts are stacked one over the other and where some lines are shared by adjacent cells, so the spacings are omitted, can have the smaller area of 2F * 3F = 6F^2.

In the 6F^2 cell, there are are 3 transistors, but they have the drain stacked over the source and one transistor is stacked above another, to minimize area.

To make a 4F^2 DRAM cell, there are various approaches, e.g. one could try to stack even more components vertically or one could go back to one-transistor cells, but in modern technology, but it is not obvious whether the much higher processing cost is compensated by the reduced die area.

Micron claims that despite the reduced area the cost would be higher, while the competitors, including the Chinese, claim the opposite.

I don't know any of the details, but dram is basically a whole lot of bits and and each bit is one capacitor and one transistor.

In the diagram for 8F Squared, there's a capacitor at every other junction between word lines and bit lines. If the lines (and inter line spacing) are 2F wide, you have one bit in a 2Fx4F rectangle, or one bit per 8F squared.

In the diagram for 6F Squared, there's a capacitor at every bit line on every other word line. If the lines (and inter line spacing) are 2F wide, you have one bits in each 2Fx3F Rectangle, or one bit per 6F squared. (I guess the word lines without bits are needed for spacing or to drive the transistor or maybe it's just illustration and doesn't mean much)

In the diagram for 4F Squared, there's a transistor at every bit line on every word line. Now you have a bit in every 2Fx2F square, or one bit per 4F Squared.

If you can make dram in all three styles with the same F, 4F squared is twice the density as 8F squared. If the F doesn't hold constant, it's squishier, of course.