Those are completely misleading, because they are not the true cell layouts.

Searching for the Micron patent on 6F^2 cells (US 6,975,531) is much more informative.

The essence of the problem is the following. An ideal memory array cell is formed at the intersection of a vertical line with a horizontal line. A line has the width 2F (i.e. metal width + spacing width), so the area of the cell is 2F * 2F = 4F^2.

Instead of that, most DRAM cells are at the intersection of 2 horizontal lines with 1 vertical line. The single line is a bidirectional data line with the value of the stored bit, while the pair of lines are a write select line and a read select line.

Using separate read and write transistors provides better performance.

The naive layout for a cell where 2 lines intersect with 1 line has an area of 2F * 4F = 8F^2.

An optimized layout where many parts are stacked one over the other and where some lines are shared by adjacent cells, so the spacings are omitted, can have the smaller area of 2F * 3F = 6F^2.

In the 6F^2 cell, there are are 3 transistors, but they have the drain stacked over the source and one transistor is stacked above another, to minimize area.

To make a 4F^2 DRAM cell, there are various approaches, e.g. one could try to stack even more components vertically or one could go back to one-transistor cells, but in modern technology, but it is not obvious whether the much higher processing cost is compensated by the reduced die area.

Micron claims that despite the reduced area the cost would be higher, while the competitors, including the Chinese, claim the opposite.

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