I thought Rosetta 2 was a purely software layer

Rosetta 2 is software, but there are design decisions made for the M-series chips that are specifically made to improve the ability of Rosetta to work in a performant way. The main one I'm aware of is the x86-TSO memory-ordering mode - most ARM chips don't support this, but the M-series have it so that Rosetta can toggle it on for x86 emulation.

I'm not sure what the total cost of these are, but it's not zero.

	▲	kbolino an hour ago \| parent \| next [-]
		There's another big one, 4K page support. The MMU can be told to set up a virtual address space with smaller, x86-compatible 4096-byte memory pages instead of the default 16384-byte pages.
	▲	mrpippy 35 minutes ago \| parent \| prev [-]
		Those are still needed for the Rosetta use-cases that are sticking around (old games, Linux binaries)