It's not the form factor itself that is the problem. LPDDR is more efficient for various reasons and cannot be on a DIMM. It physically will not work with a socket. That is the problem that LP-CAMM solves: LPDDR but still removable.

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Koffiepoeder 5 hours ago | parent [-]

You did not answer the question.

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jeffbee 4 hours ago | parent [-]

Did I not? I'm trying my best here. The question is sort of off-target, though. What I am trying to say is: 1) DDR uses more power than LPDDR; 2) LPDDR cannot work on a DIMM socket, because of its lower voltage signals, and other reasons; 3) SO-DIMMs always contain the higher power DDR; QED) if you insist on SO-DIMMs, then you have to spend more energy.

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Koffiepoeder 4 hours ago | parent [-]

Rohansi was basically asking 'why', you keep on reiterating that DDR uses more power than LPDDR, but fail to answer why this is the case. Is it clock speed? Is it voltage? Is it a protocol/specification difference? 'various reasons' is not an answer.

	▲	ua709 4 hours ago \| parent \| next [-]
		There is no physics based reason why it couldn't work. If the industry really wanted to do it they could. But they don't. The primary reason is LPDDR just has too many pins. A DDR5 SODIMM has 262 pins and is an unwieldy beast. LPDDR5 has 644 pins. LPCAMM2 really shows the trade-offs. It adds a lot of bulk and cost, and repairability hasn't been valued high enough by the market to cover that overhead for most consumers. That's why Micron exited the market they played a big part in founding. https://www.ifixit.com/News/95078/lpcamm2-memory-is-finally-...
	▲	jeffbee 4 hours ago \| parent \| prev [-]
		LPDDR is very different from DDR so I don't really feel like diving into it in this tiny box. It has its own oscillators so the CPU doesn't have to clock it while asleep; it adaptively refreshes less often according to temperature; during self-refresh the cells are charged to a lower voltage that wouldn't really work for high-speed I/O but works fine for retention.