I read the summary but not the paper and it seems like it has nothing to do with physical design. This is a means of making the elaborate/compile/simulation performance of the language faster.

Say someone wrote this code:

    wire [31:0] a, b, c;
    for(i=0; i<32; i=i+1) begin
       assign c[i] = a[i] & b[i];
    end

it sounds like this paper is about recognizing it could be implemented something akin to this:

    wire [31:0] a, b, c;
    assign c = a & b;

Both will produce the exact same gates, but the latter form will compile and simulate faster.

▲ taktoa 5 hours ago | parent [-]

In section 4.4 it discusses the effect of the technique on Cadence Genus, which is a PD/synthesis tool. My point is that you have to flatten the graph at some point, and most of the benefit of flattening it later (keeping/making things vectorized) is to do higher level transformations, which are mostly not effective.

	▲	kyboren 2 hours ago \| parent [-]
		Well, to be fair, the authors propose this thesis: "Although the vectorization of Verilog designs does not change the hardware they describe, it reduces their symbolic complexity, enabling faster and more scalable analysis and verification." Maybe it doesn't help Design Compiler turn your shitty design into gold, but faster verification is an unalloyed good.