The bigger the chip, the worse the yield.

speedgoose 3 hours ago | parent | next [-]

I suggest to read their website, they explain pretty well how they manage good yield. Though I’m not an expert in this field. I does make sense and I would be surprised if they were caught lying.

▲

moralestapia 4 hours ago | parent | prev [-]

This comment doesn't make sense.

▲

Sohcahtoa82 3 hours ago | parent | next [-]

One wafer will turn into multiple chips.

Defects are best measured on a per-wafer basis, not per-chip. So if if your chips are huge and you can only put 4 chips on a wafer, 1 defect can cut your yield by 25%. If they're smaller and you fit 100 chips on a wafer, then 1 defect on the wafer is only cutting yield by 1%. Of course, there's more to this when you start reading about "binning", fusing off cores, etc.

There's plenty of information out there about how CPU manufacturing works, why defects happen, and how they're handled. Suffice to say, the comment makes perfect sense.

	▲	snovv_crash 2 hours ago \| parent [-]
		That's why you typically fuse off defective sub-units and just have a slightly slower chip. GPU and CPU manufacturers have done this for at least 15 years now, that I'm aware of.

▲

azinman2 4 hours ago | parent | prev | next [-]

Sure it does. If it’s many small dies on a wafer, then imperfections don’t ruin the entire batch; you just bin those components. If the entire wafer is a single die, you have much less tolerance for errors.

	▲	dekhn 3 hours ago \| parent \| next [-]
		Although, IIUC, Cerebras expects some amount of imperfection and can adjust the hardware (or maybe the software) to avoid those components after they're detected. https://www.cerebras.ai/blog/100x-defect-tolerance-how-cereb...
	▲	pertymcpert 3 hours ago \| parent \| prev [-]
		You can just do dynamic binning.

▲

louiereederson an hour ago | parent | prev | next [-]

You say this with such confidence and then ask if smaller chips require smaller wafers.

▲

DocJade 4 hours ago | parent | prev [-]

Bigger chip = more surface area = higher chance for somewhere in the chip to have a manufacturing defect

Yields on silicon are great, but not perfect

▲

moralestapia 3 hours ago | parent [-]

Does that mean smaller chips are made from smaller wafers?

▲

Sohcahtoa82 an hour ago | parent [-]

Nope. They use the same size wafers and then just put more chips on a wafer.

▲

moralestapia 29 minutes ago | parent [-]

So, does a wafer with a huge chip has more defects per area than a wafer with 100s of small chips?

	▲	dgfl 10 minutes ago \| parent [-]
		There’s an expected amount of defects per wafer. If a chip has a defect, then it is lost (simplification). A wafer with 100 chips may lose 10 to defects, giving a yield of 90%. The same wafer but with 1000 smaller chips would still have lost only 10 of them, giving 99% yield.