From the paper

> footprint of 330 × 290 µm2 using the GlobalFoundries 45SPCLO

That’s a 45nm process but the units for the chip size probably should have been 330um? However I’m not well versed enough in the details to parse it out.

https://arxiv.org/abs/2503.19544

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bgnn 3 days ago | parent [-]

I'm very familiar with this process as I use it regularly.

The area is massive. 330um × 290um are the X and Y dimensions. The area is roughly 0.1 mm2. You can see the comparison on table 1. This is roughly 50000 times larger than an SRAM of 45nm process.

This is the problem with photonic circuits. They are massive compared to electronics.

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pezezin 3 days ago | parent | next [-]

Would it be possible to use something similar to DWDM to store/process multiple bits in parallel in the same circuit?

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bgnn 2 days ago | parent [-]

It isn't unfortunately as the physical size of the resonators need to match a given wavelength. So for each wavelength you need a new circuit in parallel.

	▲	pezezin a day ago \| parent [-]
		I see, that's a pity then.

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bun_at_work 3 days ago | parent | prev [-]

Is it prohibitively larger? And is the size a fundamental constraint of the technology, or is it possible to reduce the size?

	▲	adrian_b 3 days ago \| parent \| next [-]
		The size is a fundamental constraint of optical technologies, because it is related to the wavelength of light, which is much bigger than the sizes of semiconductor devices. This is why modern semiconductor devices no longer use lithography with visible light or even with near ultraviolet, but they must use extreme ultraviolet. The advantage of such optical devices is speed and low power consumption in the optical device itself (ignoring the power consumption of lasers, which might be shared by many devices). Such memories have special purposes in various instruments, they are not suitable as computer memories.
	▲	bgnn 2 days ago \| parent \| prev [-]
		Previous reply is correct. To give a feeling: micro-ribg resonators are anywhere between 10 to 40 micrometer in diameter. You also need a bunch of other waveguides. The process in the paper uses silicon waveguides, with 400nm width if I'm not wrong. So any optical feature unfortunately isn't going down as much as CMOS technology. Fun fact: the photolithography has the same limitations. They use all kinds of tricks (different optical affects to shrink the features) but fundamentally limited by the wavelength used. This is why we are seeing a push to a lower and lower wavelengths by ASML. That + multiple patterning helps to scale CMOS down.