What was the most surprising timing constraint you had to meet for the V20 bus controller? The 8088's multiclock cycles were always under specified in original datasheets and I'm curious what reality looked like.

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bit-hack a day ago | parent [-]

The bus controller was fairly straight forward. I found the timing diagrams in the V20 datasheet to be pretty easy to follow. The clock for the CPU is generated by the FPGA which I derived from a clock running at twice the speed, that made it easy to pick which clock edges I wanted to sample from or assert data for the CPU on. I did have a bug or two in there early on which meant that memory writes would not store the data I was expecting as I sampled the data bus at the wrong time. That was a tricky one as the bug would only become visible when that location was loaded from again. The CPU i'm using is rated for 16Mhz, but i've only tried to push it up to 10Mhz so far so I have a bit of margin. Some more issues might pop up if I push the speed higher I suspect. Its very stable as it is now and i've not seen any issues I could attribute to the bus handling.

	▲	rasz 7 hours ago \| parent [-]
		>I derived from a clock running at twice the speed aah, so CFG_ENABLE_20MHZ runs cpu at 10. I was surprised you could run the bus at 20MHz with this FPGA devboard, 10 makes more sense. As I touched on that in HaD comment this is not a good devboard :( It has terrible pinout https://github.com/wuxx/icesugar-pro/tree/master/schematic all 100 signals huddling together in the middle with only 9 ground pins among them. Very bad for signal integrity. Whats worse someone in China actually decided to sell it commercially :( Luckily you made it work.