Yeah, analog memory fits so incredibly well. Who cares if it's not "exact" and fuzzes around a bit if it's only used for weights and has massive efficiency advantages. Weights are never "exact" themselves, and it doesn't matter if they don't always read exactly the same. You basically just get some extra "temperature" for free!

A bit beautiful that we might end up partially going back to analog computers, which were quickly replaced by digital ones.

Their NorthPole chip doesn't look much different than the Groq LPU or Tenstorrent's hardware or even just AMD's NPU design. The tenstorrent cards have a pretty big amount of SRAM considering their price.

Here is John Backus' original paper[0], which is an easy read, but note what he calls functional programming_ has nothing to do with lambda calculus, Haskel etc... it is the APL family.

He is absolutely one of IBM's historical rockstars. IMHO they are invoking him to sell their NorthPole chips which have on-die memory distributed between the processing components and probably has value.

> In its simplest form a von Neumann computer has three parts: a central processing unit (or CPU), a store, and a connecting tube that can transmit a single word between the CPU and the store (and send an address to the store). I propose to call this tube the yon Neumann bottleneck. The task of a program is to change the contents of the store in some major way; when one considers that this task must be accomplished entirely by pumping single words back and forth through the von Neumann bottleneck, the reason for its name becomes clear.

IMHO IBM is invoking John Backus' work to sell what may be an absolutely great product but are really just ASICs and don't relate to his machine or programming language limits.

[0] https://dl.acm.org/doi/pdf/10.1145/359576.359579

Sort of? It's about locality of data; this has often been a bottleneck, which is why we have CPU caches to keep data extremely close to the CPU cores with practically zero latency and throughput limitations compared to fetching from main memory. Unfortunately now we're shuffling terabytes of data through our algorithms and the CPU spends a huge amount of its time waiting for the next batch of data to come in through the pipe.

This is, IIRC, part of why Apple's M-series chips are as performant as they are: they not only have a unified memory architecture which eliminates the need to copy data from CPU main memory to GPU or NPU main memory to operate on it (and then copy the result back) but the RAM being on the package means that it's slightly "more local" and the memory channels can be optimized for the system they're going to be connected to.

You are correct I should have specified pico2

That said AVH-lite is called lite because it is a simplified form of the arm norm.

The RP2350 can issue one fetch and one load/store per cycle, and that is that almost everything called a CPU and not a MCU will have ABH5 or better.

The “von Neumann bottleneck” was (when I went to school) that the CPU cannot simultaneously fetch an instruction and read/write data from or to memory.

That doesn’t apply to smartphones, PCs or servers even in the intel world due to instruction caches etc…

It is just old man yells at clouds

No, that's how you get SlopNet.

I skimed the repo and only found sloop. Can you point out where I can find those new architectures you talk about?