>> Through the years, imec has made considerable progress in assessing, understanding, and modeling reliability failure, paving the way to building reliable IGZO transistors with a target lifetime of five years

Five year lifetime isn't getting anywhere near my setup. Also notably absent was anything about read or write times. It sounded promising all the way up to that last paragraph.

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adgjlsfhk1 3 days ago | parent | next [-]

The read and write times are apparently in the ~10ns range which is within the allowable range for DRAM (you'll have another 50-100 from the connectivity anyway)

	▲	yvdriess 3 days ago \| parent [-]
		It would be a waste to use this to just make DIMMs. It's only transistors, like SRAM cells, so you can efficiently fab them on the same process technology and the same dies as your logic. Then again, there is wear, so either you accept a level of performance degeneration (dynamic capacity cache?) or you go to DIMMs anyway servicability.

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Dylan16807 2 days ago | parent | prev | next [-]

https://www.imec-int.com/en/articles/capacitor-less-igzo-bas...

The graph on this page is awful, but those endurance lines on the right side are going up toward a century at optimal temperature.

I think we'll have to wait and see.

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burnte 3 days ago | parent | prev | next [-]

Agreed, but remember how bad flash memory was in the early SSD days.

	▲	3 days ago \| parent [-]
		[deleted]

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mrheosuper 2 days ago | parent | prev [-]

I've watched a video about this DRAM tech, looklike the write cycle lifetime is acceptable for typical usecase