The read and write times are apparently in the ~10ns range which is within the allowable range for DRAM (you'll have another 50-100 from the connectivity anyway)

It would be a waste to use this to just make DIMMs. It's only transistors, like SRAM cells, so you can efficiently fab them on the same process technology and the same dies as your logic.

Then again, there is wear, so either you accept a level of performance degeneration (dynamic capacity cache?) or you go to DIMMs anyway servicability.