Note that this is very early work - one of the papers (the HUST one from this June) shows an 8x8 cell device, i.e. 64 bits in SLC mode.

DRAM kind of plateaued in 2011, when it hit $4/GB; since then it's gotten faster and bigger, but not appreciably cheaper per bit.

This could change if there was a way to do 3D DRAM, like 3D NAND flash, but that doesn't appear to be on the table at present. Note that this isn't the "stacking" they talk about with IGZO-DRAM, where they build layers on top of each other - it's not 3D stacking itself that made flash cheap.

Flash got insanely cheap because of the single-pass 3D architecture - it's pretty cheap to put a large number (~400 nowadays) of featureless layers onto a chip, then you drill precise holes through all the layers and coat the inside of the hole with the right stuff, turning each hole into a stack of ~400 flash cells.

The cost of a wafer (and thus a chip) is proportional to the time it spends in the ultra-expensive part of the fab. 3D NAND puts maybe 100x as many cells onto a wafer as the old planar flash (you can't pack those holes as closely as the old cells), but what's important is that the wafer only spends maybe 2x as long (I'm totally guessing here) in the fab. If it took 100x as long, laying down a few hundred layers, the price advantage would vanish.

3D ram stacking still would have significant benefits since the amount of board space taken up by RAM is significant. Quadrupling capacity per area would be a game-changer for GPUs with HBM, and could allow for a CAMM like standard to make it's way into servers.

They can do it with 3D NAND because the electrons are injected into the charge storage medium through brute force. The problem is that the capacitance scales with area. We're reducing the node size but now the aspect ratios are insane and the trenches for the storage wells are >3um high. That's over 1,000 times thicker per layer compared to NAND.