I'm not aware of any GPU that implements this.

Even the interleaved execution introduced in Volta still can only execute one type of instruction at a time [1]. This feature wasn't meant to accelerate code, but to allow more composable programming models [2].

Going of the diagram, it looks equivilant to rapidly switching between predicates, not executing two different operations at once.

    if (theradIdx.x < 4) {
        A;
        B;
    } else {
        X;
        Y;
    }
    Z;

Volta:

    ->|   ->X   ->Y   ->Z|->
    ->|->A   ->B   ->Z   |->

    ->|      ->X->Y|->Z
    ->|->A->B      |->Z

    vslt mask, vid, 4
    vopA ..., mask
    vopB ..., mask
    vopX ..., ~mask
    vopY ..., ~mask
    vopZ ...

    vslt mask, vid, 4
    vopA ..., mask
    vopX ..., ~mask
    vopB ..., mask
    vopY ..., ~mask
    vopZ ...

[2] https://stackoverflow.com/questions/70987051/independent-thr...

"Divergence" is supported by any SIMD processor, but with various amounts of overhead depending on the architecture.

"Divergence" means that every "divergent" SIMD instruction is executed at least twice, with different masks, so that it is actually executed only on a subset of the lanes (i.e. CUDA "threads").

SIMT is a programming model, not a hardware implementation. NVIDIA has never explained exactly how the execution of divergent threads has been improved since Volta, but it is certain that, like before, the CUDA "threads" are not threads in the traditional sense, i.e. the CUDA "threads" do not have independent program counters that can be active simultaneously.

What seems to have been added since Volta is some mechanism for fast saving and restoring separate program counters for each CUDA "thread", in order to be able to handle data dependencies between distinct CUDA "threads" by activating the "threads" in the proper order, but those saved per-"thread" program counters cannot become active simultaneously if they have different values, so you cannot execute simultaneously instructions from different CUDA "threads", unless they perform the same operation, which is the same constraint that exists in any SIMD processor.

Post-Volta, nothing has changed when there are no dependencies between the CUDA "threads" composing a CUDA "warp".

What has changed is that now you can have dependencies between the "threads" of a "warp" and the program will produce correct results, while with older GPUs that was unlikely. However dependencies between the CUDA "threads" of a "warp" shall be avoided whenever possible, because they reduce the achievable performance.

This flexibility of CUDA is a software facility, which is independent of the hardware implementation.

For any SIMD processor one can write a compiler that translates a program written for the SIMT programming model into SIMD instructions. For example, for the Intel/AMD CPUs with SSE4/AVX/AVX-512 ISAs, there exists a compiler of this kind (ispc: https://github.com/ispc/ispc).