▲ | nsteel a day ago | ||||||||||||||||
HBM has a very wide, relatively slow interface. A HBM phy is physically large and takes up a lot of beachfront, a massive waste of area (money) if you're not going to use it. It also (currently) requires you to use a silicon interposer, another huge extra expense in your design. | |||||||||||||||||
▲ | sroussey a day ago | parent | next [-] | ||||||||||||||||
> A HBM phy is physically large and takes up a lot of beachfront, a massive waste of area (money) if you're not going to use it. The M3 Max dropped the area for the interposer to connect two chips, and there was no resulting Ultra chip. But the M1 Max and M2 Max both did. I have yet to see an x-ray of the M4 Max to see if they have built in support for combining two, have used area for HBM or anything exotic, but they have done it before. Could you recognize HBM support in an x-ray? As for the Ultra, they used to have 2.5 TB/s of interprocessor bandwidth years ago based on M1, so I hope they would step that up a notch. I don’t put much stock in the idea of the 4 or 8 way hydra. I think HBM would be more useful, but I’m just a rando on the interwebs. | |||||||||||||||||
▲ | sroussey a day ago | parent | prev [-] | ||||||||||||||||
> It also (currently) requires you to use a silicon interposer, another huge extra expense in your design. Guess what the Ultra chips use? That’s right, a silicon interposer. :) | |||||||||||||||||
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