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What's the use case for a NOR flash that large? Even at 2 Gbit, you're probably better off with something optimized for density like eMMC.

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Neywiny 18 hours ago | parent [-]

The use is that there's often (in my field) no space for an 11.5x13 eMMC. There are some that are slightly smaller, but as you brought up the wlcsp-8, there's nothing like eMMC/high capacity NAND density scaled down. If I had the bits/mm^2 of even NAND 5 years ago, I'd be a happy camper. But that's life.

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mlyle 18 hours ago | parent [-]

There's QSPI NAND parts available; they're just annoying to use.

https://www.digikey.com/en/products/detail/winbond-electroni...

https://www.digikey.com/en/products/detail/alliance-memory-i...

There's also 9x8mm eMMC. The big issue with shrinking it further is that it tends to be a module with a separate controller doing lots of things to make the memory reasonable to use.

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Neywiny 16 hours ago | parent [-]

Yeah those are what I'm looking at, but even then we've been at 8Gb for years. Manufacturers only want SLC NAND in these for valid reasons and I guess the market isn't pushing for now. The 9x8 is useful but the 3.3v that eMMC wants means I can't power off a single cell li-ion without a boost. It's all a nightmare. Trust me I've looked for solutions, unless you know of any silver bullets that came out recently.

And as you surely know, I usually can't boot from NAND (due to the aforementioned annoyance) so I'd have a boot flash and a storage flash and that's unideal.

I'll note though that the controllers are small. You can RE the die size of a common eMMC<->NAND controller and it's much smaller than 9x8. I won't share which because I honestly don't remember if we got an NDA in place but considering they all stack dies in there anyway, I don't really see that as the size driver.

	▲	bobmcnamara an hour ago \| parent [-]
		A lot of MCUs can boot from XIP QSPI/OSPI NAND. quite a feat of compatibility engineering - they made the NAND page size match QSPI transfer sizes commonly used to populate caches, so instead of bit level reads, the flash supports only cacheline level reads, which is usually what you need for XIP anyway.