Author here: I know this is a very obscure topic, but hopefully it will be interesting to some. Let me know if there are any questions...

Reading through, appears this is mostly a manufacturing concern that goes away once the chip is actually active. Correct? The charge buildup goes away, and then there's no further need for the diode antenna.

However, second question, does any chip actually use these for anything afterward? Or are these ever built so they actually do something other than simple provide manufacturing protection?

Example, they build up charge. So then the charge build up itself is effectively used as some form of remote communication method or channel between various portions of the chip. The diode discharges and in discharging effectively acts as some form of communication transfer.

Others, or it serves multiple purposes. One during manufacturing, one after manufacturing? Safety mechanism during manufacturing, and then the charge buildup location is oscillated, purposely charged, or used as a charge outlet for some other reason?

Others, Light Emitting Diode is, kind of by the name, a diode. Any of these that basically do blinking communication or something similar? Emits light when the charge breaks down, then that is picked up and used as data transfer?

Others, not going into extensively. Tune radio and TV receivers (varactor diodes). Generate radio-frequency oscillations (like actual antennas) (tunnel diodes, Gunn diodes, IMPATT diodes).

Basically, anything other than a safety mechanism for manufacturing?

Hi Ken! Your work is extremely interesting to me and I admire the effort your pour into these articles. It's been very cool to see your die analyses ramp up to more and more complex chips over the years. The Pentium is an especially neat target since it represents a major shift in the x86 architecture towards the modern chips we have today. Never a dull moment when I see a righto link!

Your pictures give insight into such a small world, individual freaking transistors on a CPU chip! Reading textbooks and wiki is one thing, but seeing silicon spliced up and photographed up close is another. Very interesting read, and very well presented too, thank you.

Absolutely fascinating!

It’s precisely these orthogonal, secondary concerns that make every industry more difficult than people on the outside might think.

Articles like yours shed light on these challenges.

I’m reminded of a recent project working on a (small!) data warehouse where for the first time in my career I had to not only be concerned with theoretical performance of queries, such as the presence or absences of indexes, but orthogonal concerns such as the time taken to rewrite terabytes of data on disk during night ETL jobs… combining with the “change rate” of the source data.

Your article is a similar concern that only specialists in the in the industry are even aware of: it’s not enough to logically route connections — a challenging optimisation all by itself — but there are these competing physical optimisation issues as well that need to be simultaneously optimised!

Late to the show, but this only works because the deposited charge always has the same sign, correct? For instance, if the ions used are positive icons (electrons stripped), the surface elements get positively charged, and the diodes drain that charge to the substrate. But, in operation, the surface elements are negatively charged, so the diodes block. (Right? Or is it the other way around?)

How are vias manufactured, and why tungsten (I suppose it has something to do with high fusion point?).

This is amazing! How did you get the pictures?

Are these structures automatically added by most EDA tools?

(If not, why not?)

Great article!

> Note that when the chip is completed, every transistor gate is connected to another transistor's source or drain (which provides the signal to the gate)

That's a very curious assertion, which made me think a bit more (it feels incorrect at first but on a second thought it looks correct)

I would think of "pure input pins" but I suppose those have pull-up or pull-down "resistors" which in silicon are actually diodes? gateless fets?