Maybe 6 months ago. Today anyone vaguely familiar with CPU design can do it.

ltbarcly3 2 hours ago | parent | next [-]

Lol it's always cute to see the amount of confidence that people have for AI when they can't tell if the work it did is actually good.

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IshKebab 2 hours ago | parent [-]

I don't think that's quite fair - this guy is clearly quite familiar with CPU design, it's very easy to run coremark, dhrystone, etc. to get a decent idea of performance, and for verification there's a reference model written in Sail you can compare against (though tbf it sounds like he didn't). AI is good at writing large test corpuses these days too.

So I would say it is relatively easy to tell if a vibe coded RISC-V CPU is actually good today. It's not like non-vibe coded RISC-V CPUs were amazingly well verified before anyway (except Ibex anyway). Even CVA6 has had some embarrassing bugs.

I expect this is a decent RISC-V core, but I also expect I could make one just as easily.

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ltbarcly3 2 hours ago | parent [-]

I don't think chip design comes down to knocking out a theoretically correct design. Then you fab it and it can't run at more than 37mhz LOL.

I think you don't know what you don't know here.

	▲	beng-nl an hour ago \| parent \| next [-]
		I wish you’d use your knowledge to add to the discussion rather than discourage others.
	▲	IshKebab an hour ago \| parent \| prev [-]
		I do know about physical design too. Just because somebody doesn't explain every single thing in a comment doesn't mean you win the argument by highlighting something they didn't mention.

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varispeed 2 hours ago | parent | prev [-]

and a bit of cloude:

"Make me an OOO RISC-V core in SystemVerilog. No mistakes."

I am somewhat of vaguely familiar with CPU design myself.