It's a bit crazy that the LLM / reverse anything age doesn't seem to have hit FPGA world much. I guess not a lot of folks super eager to play with their $10k++++ devices.

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aseipp 2 days ago | parent [-]

You can buy Agilex devices for like $100 now. They're Altera's primary chip family at this point in every device range. You can also use Quartus for free on these devices and even download it all through Docker. Knock yourself out.

The reality is just that it's a lot of work, and Agilex is probably an order of magnitude (or two orders) more complex in scope than any existing FPGA with reversed or open specs. It's going to require a lot of expertise even with superhuman assistance. Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience. If people are going to Claude shit out in the EDA space I'd frankly rather have them work on more important day to day mundane things that are still lacking but important, eg improved performance, power analysis/floorplanning, sdc/constraint based clock synthesis and related tools, etc.

And yes, breaking your device is also a risk for some features too (eg Lattice ECP5 bitstream encryption has never been RE'd since it requires blowing fuses.) But the actual problem requires far more expertise than having Claude reverse engineer gameboy games.

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duskwuff 2 days ago | parent [-]

> Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience.

The terrible Fmax on GateMate is specifically a result of its "quirky" design. There's no dedicated clock network on the part - clocks have to be routed through fabric just like everything else. Running those signals everywhere consumes routing capacity and incurs delays; the resulting clock skew is awful.

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imtringued 2 days ago | parent [-]

That type of design seems highly resistant to classic fmax raising techniques like pipelining because pipelining can't fix clock skew.

	▲	Paul_Clayton 4 hours ago \| parent [-]
		A pipeline can tolerate clock offsets. E.g., an ALU like the Pentium 4's staggered ALU but within "a single clock cycle" might allow the more significant input bits to arrive at a time offset relative to the time for the first bits of inputs. Parsing variable length encoded instructions has a similar "carry propagation". Similarly, different stages might use different amounts of the cycle. Grid network routing can also localize time synchronization. Getting the clock routing delay to approximate the delay that is designed to be tolerated seems likely to be rather tricky, but I think clock offsets from imbalanced travel distance do not have to make all of that time wasted. I might well be wrong as I am only aware of some very general concepts of hardware design. Even in my ignorance, I am aware that theoretically possible in some cases is not the same as practical/worthwhile in general.