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▲ abijahkaj 3 hours ago

I mentioned in the top comment that Koppar generated the board and that the first batch is about to be ordered, so no detective work needed there.

I'm just as skeptical of blind AI hardware output as you are, which is why I audited every net against the datasheets and put all the flaws in REVIEW.md in the repo before ordering: - The 0.33 mm RF trace came out to ~35 Ω instead of 50 Ω and hopped layers through vias (I included Pi-matching pads to tune it on the bench). - The 3.8 V buck converter was placed too far from its inductor, and the 1.37 mm power trace is narrower than Quectel's 2 mm recommendation (~100 mV drop at 3 A). - The SIM socket (J2) is oriented inward, which is annoying mechanically.

5 bare boards + 2 PCBA units are currently being ordered at JLCPCB, and I'll order the EC25-EUX modules separately to hand-solder onto U8 since JLC was out of stock.

Since the KiCad files are in the repo, if you spot a specific net or pinout error that will brick bring-up, let me know so I can bodge-wire it next week.

▲drum55 3 hours ago | parent [-]

The PCB looks super weird, what is going on here?

https://files.catbox.moe/nijoin.png

https://files.catbox.moe/suazr4.png

They sort of look sensible until you look closer and then the whole board is fever dream autorouting.

▲cowlevel 2 hours ago | parent | next [-]

they answered with AI and got flagged for being AI. You can turn on showdead in settings to see it but there's nothing of value in their comment really.

▲ 3 hours ago | parent | prev | next [-]
[deleted]
▲abijahkaj 2 hours ago | parent | prev [-]

yeah it's raw output from the router i'm coding without a trace smoothing pass yet, so it draws ugly jagged steps. looks bad to a human layout engineer, no argument there. either way it won't stop it from working, the electrons don't care how ugly the bend is at 2 MHz. just want to see if it boots when the jlcpcb parcel lands.

edit: idk why my comments are being [flagged], i've written to hn but the issue is apparently still there