Using multiple CPUs for encoding goes way back. The early (1994) C-Cube MPEG-1 and MPEG-2 real-time encoders for DirecTV were built with 8 chips running in parallel (out of necessity since they were only 60 MHz processors) to encode 704x480. Each chip encoded a slice of the image and an auxiliary bus was used to send reconstruction video between chips so that motion vectors could cross chip image boundaries.

Here's a picture of the VME bus development board. It was a two board sandwich to support 10 chips in parallel (only one board pictured).

https://www.w6rz.net/scorpio.jpg

The first real-time HDTV encoders for terrestrial digital television (ATSC) were built by Harris using an IBM encoder chip. It took 6 chips to encode 1920x1080. The IBM chips didn't have an auxiliary bus, so you could see motion vectors limited to chip image boundaries (in this case, 6 tiles arranged like so).

  -------------------------
  |       |       |       |
  |   1   |   2   |   3   |
  |       |       |       |
  -------------------------
  |       |       |       |
  |   4   |   5   |   6   |
  |       |       |       |
  -------------------------