How so? FEOL is pretty much the same, BEOL is almost the same save TSVs, the packaging tech is different and more advanced, but not exactly 1:1 comparable. Do TSVs really occupy 3x the area of DDR IO's?

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Const-me 4 hours ago | parent | next [-]

See remark on the slide 11: https://www.servethehome.com/micron-evolving-memory-architec... That presentation is by Micron.

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Karliss 3 hours ago | parent | next [-]

It doesn't really say that it needs to use 3x more area, but that 3x more gets consumed due to "advanced packaging and manfuacturing complexity". Which doesn't properly explain why it consumes 3x more and could simply mean they have a bad yield and 2/3 produced is garbage.

	▲	bob1029 3 hours ago \| parent \| next [-]
		> 2/3 produced is garbage. This might not be far off the mark. You are irreversibly linking the fates of these devices after a certain stage of manufacturing. If something goes wrong at final packaging time, you lose all dies instead of one.
	▲	tliltocatl 3 hours ago \| parent \| prev [-]
		Yea, that's the question. Yield situation can improve. Area overhead would not improve short of a completely new and incompatible tech.

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skavi 4 hours ago | parent | prev [-]

direct link: https://www.servethehome.com/micron-evolving-memory-architec...

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tliltocatl 4 hours ago | parent [-]

Yuck. Time to build an xSPI/HyperRAM workstation (if only these had multi-bank chips).

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buildbot 3 hours ago | parent [-]

Sadly the $ per byte of xSPI and HyperRAM quite high

	▲	tliltocatl 3 hours ago \| parent [-]
		Yes, but enough to run a text editor, or even a mechanical CAD. Not an LLM, but that's the point!

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monster_truck 4 hours ago | parent | prev [-]

3x is a reasonable figure. They are not literally that large, though.