| ▲ | zero_shift a day ago | ||||||||||||||||||||||
I have been prototyping some network proxies in a largely "vibe coded" fashion and it has been a mixed experience. It has definitely accelerated my learning: through the process of writing rigorous plans, I have learned so much about network programming... the intricacies of HTTP2, how to design a fast MITM proxy, performance pitfalls in SSL... These are things I studiously avoided learning for a decade, now demystified, mostly through Claude patiently rendering many figures and diagrams. And with Fable, I was able to ship a working Envoy Rust extension in a one-shot. On the other hand, my grasp on the details is tenuous. Every so often the agent can't progress and I am stuck for ideas, hitting different prompts like they were slot machines. I forget how to solve problems by myself. I can feel myself becoming supine and dependent on something I know is going to become more expensive, a dependency AI vendors will seek to exploit. It has happened quickly. I do not really consent; it is forced on me by my employer. | |||||||||||||||||||||||
| ▲ | kragen a day ago | parent [-] | ||||||||||||||||||||||
One thing I may try this week is typing in all the code myself. With the level of back and forth that I've been happy with so far, Claude Pro seems to only be able to produce about 1000 lines of code a day in two or three five-hour sessions. I can totally type 1000 lines of code in a couple of hours if no problem-solving is needed. So maybe I'll look at Claude's code, switch screens to my editor, and type until I don't know what to type, and repeat. Obviously there are higher-level design issues that I might not notice while engaging with the code at the byte-by-byte level, but I won't have the embarrassing problem I had a couple of weeks ago where duck.ai wrote me a CPU in Verilog, and after I tested it, I tried to write something in Verilog myself and couldn't even figure out how to write a syntactically correct XOR-gate module. (Verilator's parse errors are not designed as a Verilog tutorial, it turns out.) | |||||||||||||||||||||||
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