If we exclude short-term shortages then no. The cost to make a wafer hasn't really changed. Larger wafers improved costs but that's about it AFAIK.

Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).

Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.

It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.

But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.

It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.

Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?

MRAM is 1T, non-volatile and supposedly has nanosecond-scale write times so it naively seems like it'd be an ideal SRAM replacement. But I guess shrinking MTJ is more difficult than other components or there are some other limitations.

> 1T-1C SRAM

Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.