Incredible amount of determination, but you really did make it hard for yourself!

You can install librelane to get the whole open silicon tool suite and the sky130 PDK. Circuit extraction can be done with magic. Going from a spice netlist to verilog netlist is pretty mechanical and not a hard transform to write. You almost immediately have something that can be simulated and a good baseline for further reversing.

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__atx__ 4 hours ago | parent | next [-]

> Circuit extraction can be done with magic.

So that was the missing part for me! I did it from scratch (with custom Python script with gdstk and shapely) (the GDS file does have the cells annotated, so not a big problem but still). I was thinking about scripting the "trace net" tool in klayout but decided that's going to probably bring its own can of worms...

	▲	vzcx 4 hours ago \| parent [-]
		You can give the cell instances a stable name by setting GDS property 98, which I learned about from my reconnaissance of the puzzle author's github and sky130 visualization tool. This way I was able to spot check a pass over the netlist that broke up the regions into a hierarchical design. I'd like to do a full writeup but haven't had the time.

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anitil 3 hours ago | parent | prev [-]

> Incredible amount of determination

That's very kind of you. At some point I had put so much of myself in to it that I was in too deep and the only was out was to keep digging.

I'll take a look at librelane thanks!