To my understanding, the RP2350 has two ARM cores and two RISC-V cores, the two pairs are separate, and only one architecture can be used at a time on the chip.

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dmitrygr 12 hours ago | parent [-]

nope. two "slots", each selectable from {ARM, RISCV}. In each, you pick one. so you can configure it at two arm cores, arm + riscv, or two riscv cores. dual-arch is possible, if you desire it

	▲	bmitc an hour ago \| parent [-]
		Thanks, and yea, you're right. Their top-level copy muddies the waters on this and makes it sound like what I wrote, but indeed, from their datasheet: > The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. > Practical applications for this are limited, since this requires two separate program images. The two cores interoperate normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by an Arm processor performing ldrex, strex instructions and a RISC-V processor performing amoadd.w instructions, for example. > Hardware supports debugging for a mixture of Arm and RISC-V processors, though this may prove challenging on the host software side. Debug resources for unused processors are dynamically marked as non-PRESENT in the top-level CoreSight ROM table.