Apple puts the NAND flash controller on package, so it cooled as part of the SoC/CPU as they share an IHS. Given it is part of the fabric it only has to maintain signal coherence on millimeter to micrometer scales, while enterprise/consumer NAND PCIe have to adhere to standards which force them to signal at 800-1200mV and keep that signal stable for centimeter scale distances.

Basically, Apple gets to cheat because they shove everyone onto the same IC & make the OS that runs on this SOC.

They wound up with this design because these chips are descendent from the iPhone 4, where the whole motherboard was 1 inch.