To add to that, the only way I see proof of absence of timing channels is by proving both the software and the hardware design side by side, and then the proof would hold only for a specific core. Something that would look both at the code manipulating secrets and at the Verilog for the specific core/memory chips. I've not been working in that space in a long while but AFAIK such a thing is nowhere near ready. I suspect it will be a lot easier if the hardware design is optimised for provability, which won't be good at all for performance. But there are plenty of contexts where security matters a lot more than performance (SMC, BMC, RoT and co at the very least).

And then you'd need assurance that the Verilog is faithfully transcribed in the silicon, which is a can of worms in itself.

In general you don’t need things that fancy. Instead, you can take

1. Some known set of architectures, with

2. Some known set of (constant time/variable time) operations

And then prove things about programs written against those architectures. See for example

https://github.com/PLSysSec/FaCT

That being said, practically the operations that are variable time are known, and are mostly* the same on all modern architectures. In particular

1. Branching on a secret-dependent variable, or

2. Indexing an array with a secret-dependent index, or

3. Some architecture specific operations (typically things like division, occasionally things like multiplications/shifting).

I don't think it needs to be so dramatic. You could have a proof that the algorithms don't contain data-dependent logic, and perhaps ensure that no data-dependent instructions are generated; and that all branches have the same number of instrution-cycles (adding padding if not). You'd then simply rely on the architecture-specific instruction timing differences to be respected by the compiler.

Would something like this guarantee that no side-channels are possible on any architecture? Perhaps not, but it would still get you most of the way there.