It's more the economics of what sells that lets the power hungry monsters thrive. If you can tape out one chip design, and one gives you 1 TOPS and the other is 5 TOPS, the sales will go to the 5 TOPS because power is a downstream cost. That being said, it's only a matter of time before both chips are maximum TOPS and the only differentiator is power. My latest simulations are showing a competitive design around 70W, but I'm still confirming it and it would really be beneficial to do some data gathering tapeouts at larger nodes to feel like it's worth the risk of more expensive nodes.

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brcmthrowaway an hour ago | parent [-]

Systolic hardware?

	▲	skyberrys 37 minutes ago \| parent [-]
		Race logic with pulses, it's a descent of systolic arrays. There is less of an array shape and more about time.