| ▲ | wuschel a day ago | |||||||||||||||||||||||||
I understand that they used Claude to create some sort of verification code and test environments from circuit-design information, verification programs, and protocol specifications. But isn't precisely this quite risky due to the statitical nature of LLMs? I would have thought that they rather operate with very rigid test suites based on such software like F*, Coq, and whatnot. Can someone with understanding of the process chime in here? Here is the text snippet from the original korean article. Indeed the information was misrepresented: "Customer-specific SoC verification work, which Usually takes Over a month, was completed in just two days. A second-year employee completed a USB model development that previously takes a month in a single day". | ||||||||||||||||||||||||||
| ▲ | Junk_Collector 21 hours ago | parent [-] | |||||||||||||||||||||||||
From what's described in the article they are using it to write the process code. That is, control code for setting the states of the SOC under test and the test equipment, then recording the data that the test equipment would measure. It can be a pain to do because each SOC and piece of test equipment might have it's own control language, drivers, different data formats, etc. This usually all has to tie back in to a local (self hosting is the norm) cloud service for quality tracking and some 3rd party enterprise software from companies like Cadence. The test equipment would be something like a Keithley Parametric wafer tester, which is actually an entire rack of equipment glued together by 3rd party code with semi-open APIs. It's not uncommon to make thousands of measurements on an SOC during verification and then process engineers work to reduce the measurement count to just the critical ones for manufacturing. | ||||||||||||||||||||||||||
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