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| ▲ | btown 6 hours ago | parent | next [-] |
| There are many industries and situations that will pay absurdly high multiples on API rates for low latency access. Anything remotely related to finance, deal flow, or trading, including the development and checking of Excel financial models. Live analytics that can be delivered mid-meeting to C-suite executives, or ultra-luxe dealmakers who need answers while on a live call. Intelligence and defense, where milliseconds matter. With the tool calls that can be done, you're not pricing this against an executive assistant or pocket analyst - you're pricing this against the ability to have an entire Bourne Identity style analysis room at your disposal. The limited inventory will go to the people for whom money is no object. |
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| ▲ | combustion 6 hours ago | parent [-] | | Please write your own posts | | |
| ▲ | phoghed 2 hours ago | parent [-] | | Please provide some, any, evidence or reasoning for your accusations. Otherwise it’s just lazy. I know shallow dismissals is kind of HN’s thing, but come on, a little effort please. Currently, your comment is just as much slop |
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| ▲ | petu 6 hours ago | parent | prev | next [-] |
| I have no idea, but I've assumed that batching can't work on Cerebras. Batching works because of severe memory bottleneck, but Cerebras whole thing is serving models out of "L1 cache" (?). |
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| ▲ | philipportner 6 hours ago | parent | prev | next [-] |
| You'd need hundreds of GB alone for the KV cache of each user. For something like LLama 3 405B you need ~67GB at ~130k tokens.
A single CS-3 has 44GB on-chip sram. So, afaik, Cerebras are optimizing for ultra-low latency batch=1 inference. https://newsletter.semianalysis.com/p/cerebras-faster-tokens... goes quite in-depth. |
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| ▲ | jaggederest 6 hours ago | parent | prev | next [-] |
| They're cache limited, almost certainly, so more slower sessions doesn't solve the problem - you still have to load and unload the whole cache hierarchy at some level and that's a network bandwidth and memory bandwidth problem between the external systems and the waferscale chip. Also worth looking into how they do cooling for it, because that's kind of absurd and awesome as well. |
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| ▲ | dwohnitmok 6 hours ago | parent | prev | next [-] |
| > I don't think I understand why they aren't leveraging the increased speed to do batching to serve more customers at a "normal" tok/s. There's some technical hypotheses about it that other people are offering. But also from a business perspective, it totally makes sense not to go any sort of batching play. It's really valuable and very clear to consumers to make your pitch entirely about lower latency rather than higher bandwidth. There are so many scenarios that are latency-constrained that will be difficult or even impossible for someone even with fleets of high-bandwidth compute to compete with you on. Very easy pitch to sell a customer who asks what differentiates you from other companies: you pay us a premium for lower latency than anyone else. |
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| ▲ | fragmede 5 hours ago | parent | prev | next [-] |
| To use a car analogy, they built. Ferrari and technically you could put a tow hitch on it and go slow and carry a bunch of cargo instead of 1 passenger and go real fast, that's just not what they've built. There's one really fast core to send tokens at and get tokens back out at insane speeds. |
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| ▲ | porridgeraisin 5 hours ago | parent | prev | next [-] |
| Cerebras is a large plate sized chip. It has 50GB of SRAM, and few hundred K simple cores that can access that SRAM really fast. I don't know semiconductors well, but I understand that the same manufacturing technique that makes this huge chip possible, on the flip-side limits inter-chip communcation bandwidth. In cerebras, it is 150 GB/s (compared to nvlink's 2TB/s or groq's similar). One way large models are served on a bunch of cerebras chips is by essentially distributing layers' weights across chips. Few layers's weights per chip - as many as the KV cache + activations + weights will allow. You use pipelining to hide the latency of the inter-chip 150 GB/s link. On GPUs, you amortize the cost of loading weights from HBM to SRAM across multiple users - thereby making it cheaper _per_ user. But here, there is no such amortization. The weights are already there. It is the activations that stream through. You _could_ do batching/continuous batching, but that would just service more users at lower token/s each without any amortization of fixed cost, due to fixed cost (loading weights) being non-existent. |
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| ▲ | UltraSane 5 hours ago | parent | prev [-] |
| Because companies are willing to pay proportional to (tokens/s)^k for some value of k >1 |