| ▲ | jcranmer an hour ago | |
The post is kind of vague on the IR you're targeting. Can you give some examples of what the SIMD-ized IR looks like, and how it maps to the target PTX? | ||
| ▲ | the__alchemist an hour ago | parent | next [-] | |
I'm confused too. How does this fit between these approaches for paraellization:
It looks like from the code samples like maybe a cleaner syntax for writing code on the GPU than CUDA kernels? E.g. without mucking with serialization, host and device by abstracting over it? And inspired by core::simd. (Good choice if so, in the interest of standardizing on syntax; I did this for my x86 SIMD vector/quaternion lib as well) | ||
| ▲ | LegNeato 12 minutes ago | parent | prev [-] | |
Didn't want to go into crazy detail in the post. Each family of operations is a trait parameterized by the operation itself:
Call sites name the operation:
Operations like Sum, Max, ReduceXor, Inclusive, and Exclusive are all distinct types.As mentioned in the post, execution shape is typed too. A static shuffle takes its control as a type-level constant, and the shuffle mode constrains which controls are expressible:
For an example of errors caught, a warp-scoped executor for a device-scoped barrier is a compile error:
Strip mining is typed on the amount of work and the lane capacity, and it hands back one chunk at a time along with the predicate saying which lanes live in that chunk:
Hopefully that gives the flavor of it. | ||