2 to 3 months optimistically assuming everything goes smoothly and is fully automated.

6 months or even a year if something goes wrong in the fabrication process and you need to update things.

If they do more standard asic design, it could be a lot longer as the design needs to be validated on an FPGA cluster, which would necessarily need to be very big for something like a LLM. Easily up to 2 years.

There's a reason chatjimmy isn't demonstrating newer models and why they only show of an 8B model.