ASICs may be too slow to iterate. If we want to close the development loop faster, I think FPGAs are a way to do so. With everything moving so fast nowadays, by the time the ASICs are ready for production, they could be already outdated, so FPGAs could be a quick way to test some novel designs, with or without LLMs' help.

If the ASIC runs a model 100x better (faster, cheaper, less energy, etc.), it will remain competitive on any task for which frontier models don't improve as quickly. Any task for which current models are "good enough" arguably fall in this category. We just need to cross a threshold in terms of how many such tasks there are and their economic value. Also worth pointing out is that there's probably a lot of latent uses of LLMs, currently unexplored, that would be enabled specifically by a very low latency. Right now, I'd feel comfortable taking the risk.

The tech that makes sense here is structured ASIC