There was also a long piece by a former Intel chip designer who was incredulous about how much the Itanium team was promising numbers based on a very few hand-scheduled routines for FPU-limited code. I think there’s a solid argument that the design just wasn’t based on a correct understanding of what most CPUs did and over-indexed on the most performance-sensitive HPC code. I once helped run some HPC code on a test Itanium system and even there it was just so easy to fall out of the only patterns which performed well and end up slower than older Pentiums even before factoring price into the evaluation.

> I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on".

https://www.sigmicro.org/media/oralhistories/colwell.pdf

> Davidson also pointed out two areas where academic research could create a blind spot for architecture developers. First, most contemporary academic research ignored CISC architectures, in part due to the appeal of RISC as an architecture that could be taught in a semester-long course. Since graduate students feed the research pipeline, their initial areas of learning frequently define the future research agenda, which remained focused on RISC. Second, VLIW research tended to be driven by instruction traces generated from scientific or numerical applications. These traces are different in two key ways from the average system-wide non-scientific trace: the numerical traces often have more consistent sequential memory access patterns, and the numerical traces often reflect a greater degree of instruction-level parallelism (ILP). Assuming these traces were typical could lead architecture designers to optimize for cases found more rarely in commercial computing workloads. Fred Weber echoed this latter point in a phone interview. Bhandarkar also speculated that the decision to pursue VLIW was driven by the prejudices of a few researchers, rather than by sound technical analysis.

http://courses.cs.washington.edu/courses/csep590/06au/projec...

> http://courses.cs.washington.edu/courses/csep590/06au/projec...

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It's doubly funny knowing that basically nobody bothers doing these kinds of workloads on CPU if they can help it. And everything you have to do to get GPU floating point performance also makes GPUs really, really bad for normal CPU code. Hell, at one point AMD actually was shipping VLIW for shader code...