It is not feasible for DRAM (or the memory controller) to maintain a fully accurate simulation of DRAM. If it was easy they'd have done it.

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gpm 2 hours ago | parent | next [-]

It doesn't need to be fully accurate, merely always conservative. It's a question of cost (how much performance does the conservative estimate waste) not feasibility.

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inigyou 3 hours ago | parent | prev | next [-]

Okay then refresh the whole thing and not just a single row whenever TRR is triggered.

Or refresh the whole thing after a certain number of row activations.

Or interleave activations with refreshes. Say, after every 5 activations, refresh the next row in the refresh cycle.

I'm not a DRAM expert. They can figure it out. I promise if you refresh the whole chip after every row activation you won't have rowhammer. It'll be too slow though. Somewhere in between is the fastest point where there isn't rowhammer.

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bell-cot 2 hours ago | parent | prev [-]

It doesn't need to be a fully accurate simulation, any more than your car needs a fully accurate ICE simulation to decide "Change the engine oil".

Just count accesses to each row, and refresh the adjacent row(s) when some limit is reached.

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inigyou an hour ago | parent [-]

Half-Double is an attack where you hammer the rows 2 spaces away so that the automatic refresh on the rows 1 space away is what actually hammers the target row.

	▲	bell-cot 38 minutes ago \| parent [-]
		Yes? When a given row's counter hits the limit, you refresh every other row which your actually-competent testing has shown might maybe possibly be compromised by that activity. Same as a good car's computer doesn't make a bunch of rosy assumptions about whether the oil needs changing or not - the automotive engineers actually do their jobs, test the crap out of their engine designs, and base the oil-change criteria on the real-world test results. (JIC: "Adjacent" has a range of meanings in English. Those go from "the singular closest neighbor, within further constraints on type, orientation, etc." to "relatively close to by some metric". But I am not an EE, let alone a chip architect, to know the "real insider" lingo here.)