>The primary source of uncorrelated bit-flips is, effectively, cosmic radiation.

This gets said a lot but with little evidence. The mario speedrun bit flip has been replicated with marginal connector insertion.

https://youtu.be/vj8DzA9y8ls

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metadat 2 days ago | parent | next [-]

Engineering computer memory to work in space is a whole field of study, see Radiation Hardened memory. The main physical difference about space is the radiation profile and radiation induced memory upset.

Are you disputing that the Earth's atmosphere absorbs and reduces the amount of ambient cosmic radiation? Or where is the skepticism coming from?

	▲	willis936 2 days ago \| parent [-]
		I am disputing that cosmic ray showers are the obvious dominant source of terrestrial DRAM bit flips.

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adrian_b 2 days ago | parent | prev | next [-]

There is a lot of direct evidence from increased error rates in computers on airplanes.

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willis936 2 days ago | parent [-]

That's a much weaker statement than "the primary source of uncorrelated bit flips is cosmic radiation".

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adrian_b 2 days ago | parent | next [-]

Cosmic radiation is always a source of errors for any kind of DRAM.

Whether it is the primary source of errors, depends on the design of the DRAM die.

In a badly designed DRAM there could be many other error causes.

The designers of a DRAM certainly attempt to minimize all the error causes that they can control. If they succeed, the cosmic radiation would remain the primary error source.

Without access to internal documents of the DRAM vendors, we cannot know if they have indeed minimized all other error causes.

In modern DRAM chips, a major error cause can also be the disturbance of some memory cells when some other cells are accessed in their neighborhood, which is the basis of the Rowhammer attacks, but which can also happen during the normal use of the memory, when certain access patterns happen by chance.

The DRAM vendors do not provide details about the behavior of their devices, with the hope that this makes harder the task for someone who wants to design a variant of the Rowhammer attacks, but this also makes impossible for the owner of the memory to predict whether an application program will not perform by chance an access pattern that will unintentionally flip some memory bits, which without ECC will not be detected and corrected.

	▲	etbe 2 days ago \| parent [-]
		Companies making DRAM have no incentive to make the best products theoretically possible, they just want them good enough to not get many returns and avoid the risk of a class action lawsuit if a significant pattern of problems appears. Avoiding returns for ECC DIMMs is a harder challenge when they are used in an environment where the server will have a management system that tracks errors over all time and when there might be a network management system tracking all errors over all systems. Avoiding returns for non-ECC DIMMs is easy when a few errors per month won't be noticed by most users who assume that Windows always crashes anyway. Has any DRAM company tested chips and made non-ECC DIMMs from the ones that have lower quality? As an aside are the 2^N*3 sizes of DDR5 DIMMs (like 24G and 48G) made from chips that had errors in one section and got reconfigured to have 3/4 the capacity to not use the bad parts?

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exmadscientist 2 days ago | parent | prev [-]

The word "uncorrelated" is doing a lot of heavy lifting in that claim. Most DRAM error sources are pretty clearly correlated, if you're paying any attention.

	▲	2 days ago \| parent [-]
		[deleted]

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wmf 2 days ago | parent | prev [-]

AFAIK it's been documented by Los Alamos since they're at high altitude.