This guy is right. Physical memory isn't flat. Every system with more than a few cores is NUMA. There are caches and cache lines. Memory channel interleaving. Ranks and banks and rows. Each DRAM chip keeps the last selected row and can access addresses within that row more quickly even if other accesses to other chips occur in the middle, unless a refresh cycle occurs.

It's all a layer below even OS programming. It's configured at the BIOS level and then performed in hardware. But that's the point, isn't it? Virtual memory is below the application programmer, too, but here we're chastising him for not understanding it. If we do that, shouldn't we equally chastise people for not understanding physical memory? Or speculative execution? Or head seeking and servo tracks? Or Ethernet line coding?

Even NUMA is a "flat space of contiguous addresses". There's no bank switching or whatever. Yes, the access times are non-uniform, but that's orthogonal. The point of my comment to the OP is that if you're going to be super-pedantic about this stuff, you need to get your terminology right.