| ▲ | WithinReason a day ago | ||||||||||||||||
...not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache. What is this feature for? When do you need it? | |||||||||||||||||
| ▲ | averne_ 7 hours ago | parent | next [-] | ||||||||||||||||
The explanation is missing that the hardware also notifies you of modifications, which makes it useful for implementing cross-cluster synchronization primitives. Compare to MONITOR/MWAIT on x86: https://www.felixcloutier.com/x86/mwait#mwait-for-address-ra... | |||||||||||||||||
| ▲ | dragontamer a day ago | parent | prev [-] | ||||||||||||||||
GPUs are absurdly SMT. Like 8 threads or 10 threads (or tracked instruction pointers) per hardware instruction execution unit (for AMD, the Workgroup Processor, WGP) I have to imagine that some kind of queue or data structure would benefit from this information. Especially with server GPU tasks staying resident inside of a WGP for literally hours at a time. | |||||||||||||||||
| |||||||||||||||||