Due to the thermal budget, most of the silicon design is constrained to a 2D layout. So the Memory is competing with logic for layout. Now we stack logic in the backend between metals.

We fabricated 2T0C DRAM arrays with a 3D monolithic structure. That's a must-do.

Why 28nm? Because it's cheap, widely available, and already gives us enough performance to beat Nvidia Vera Rubin. We have a road map, scaling it down. https://www.phantafield.com/whitepaper#6-scaling-roadmap

> 2T0C

2 transistor zero capacitors

See last paragraph (3.) of another comment for context: https://news.ycombinator.com/item?id=48713803