My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?

Correction: it’s not stacking. They do things like FinFET (turning the gates in the third dimension) and gate-all-around which increases the density of transistors per unit area. But they don’t have layers of transistors. At least in the logic and analog processes.

If they're adding a dimension, the marketing should reflect that.

I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"