Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input.

The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?

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kens a day ago | parent [-]

Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits).

If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifters. I don't know how the circuit area compares between the two approaches--two more complex stages vs six simpler stages--but I suspect the two-stage approach wins.

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xenadu02 a day ago | parent [-]

Wasn't this also one of the last chips laid out by hand (literally the masks were cut and laid out physically)? Or am I thinking of something else?

I sometimes wonder if some design decisions were made on that basis.

	▲	kens a day ago \| parent [-]
		CAD was a very incremental process. Early chips were drawn by hand and the Rubylith masks were cut by hand with the help of a Coordinatograph. Later, Intel used a Xynetics plotter to cut the Rubylith. By 1974, layouts were digitized with a Calma GDS I so repeated cells could be handled automatically. By the time of the 8087, there was a lot of automation. You might think that the 8087's shifter would be a regular grid, easy to lay out by hand. It turns out to be very optimized and irregular. (I traced it out by hand and it was a pain.)