I designed a nibble-oriented CPU in Verilog to build a scientific calculator

My dad worked for HP from the mid-1970s through the mid-1990s. Needless to say, I used HP calculators in high school and college. The best things about having an HP calculator were the solid physical construction (the buttons on the 11C and 15C were awesome), the accuracy, and the fact that whenever your classmates asked to borrow your calculator they would recoil in horror when you asked them whether they knew RPN. Nobody borrowed my calculator. Anyway, I love this project.

	▲	phkahler 12 minutes ago \| parent [-]
		I still have my dads old HP with the glowing red letters and all the functions. Not sure if we still have the charger. Not sure the battery is any good, but the calculator worked fine last time it was turned on decades ago. Any idea if this can be made to function again?

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wewtyflakes an hour ago | parent | prev | next [-]

If the CPU is nibble-oriented, wouldn't that mean that that is its byte size?

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joemi 28 minutes ago | parent | next [-]

Are you trying to make a pun with byte/bite relating to nibble? Because that's actually where the term nibble (referring to 4 bits) comes from, so I'm not sure such a pun even counts as a pun anymore. Or am I misinterpreting your comment?

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hvs 39 minutes ago | parent | prev [-]

A byte is always 8 bits. The word you're looking for is `word-size` which, in this case would be 4 bits.

	▲	jlokier 32 minutes ago \| parent [-]
		A byte is not always 8 bits on old machines, though it is standardised as 8 bits nowadays. This is why network RFCs talk of "octets", to avoid the ambiguity. Octets are always 8 bits. https://en.wikipedia.org/wiki/Octet_(computing)

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gdevic 3 hours ago | parent | prev [-]

The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch.

The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.

What the project covers:

- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a FAULT state for microcode debugging

- CORDIC for trig functions, verified to 14 significant digits

- Two-pass assembler in Python (~700 lines)

- Verilator + Qt framework: same Verilog source runs in simulation, as a desktop GUI debugger, as WebAssembly, and on real hardware

- Scripting language on top of the microcode for adding functions without touching hardware

- Custom PCB (EasyEDA/JLCPCB), battery, charging circuit

Write-up: https://baltazarstudios.com

Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the...

	▲	VLM 2 hours ago \| parent [-]
		Ironically the Z80 is a nibble ALU. That's why its so slow compared to the competition, an 8 bit add on a "2 MHz" Z80 takes as much clock time as a 8 bit add on a "1 MHz" 6809.