| ▲ | IshKebab 5 hours ago | |
It isn't because no ISA implements add like that, so there's always performance on the table if you check every time, and people would probably endlessly moan about how Rust is 20% slower than C on this add-heavy microbenchmark. That said you can enable overflow checks in Rust's release mode. It's literally two lines:
I wonder if it would make sense for ISAs to have trapping versions of add and subtract. RISC-V's justification for not doing that is that it's only a couple more instructions to check afterwards. It would be interesting to see the performance difference of `overflow-check = true` on high performance RISC-V chips once they are available. | ||
| ▲ | codedokode 3 hours ago | parent | next [-] | |
I think it is 3 extra instructions on RISC-V if you add signed numbers. So 1 addition (the most popular operation) turns into 4 instructions. What are those people thinking? I generally like RISC-V but this part in my opinion, is wrong. They should just have added "overflow enabled" bit to the add instruction. | ||
| ▲ | tialaramex 5 hours ago | parent | prev | next [-] | |
It does seem like "What if we offer checked integer arithmetic operations?" is a cheaper experiment than CHERI's "What if we mechanically reify extent based provenance"?" | ||
| ▲ | kps 4 hours ago | parent | prev [-] | |
> It isn't because no ISA implements add like that MIPS does (did?). And VAX, IBM/360, .... | ||