This wccf article also doesn't do a great job of describing, but the third slide it shows is very illustrative: rather than stack horizontally it stacks dram on its side. https://wccftech.com/intel-zam-memory-threatens-hbms-ai-thro...

I thought this was going to mean each stack was able to directly talk to the controller, since all stacks are resting on an interposer thing. But actually there is still a logic controller slice at the bottom of the stack, not at a right angle to the stack.

Instead of HBM microbumps between layers there is a more compact/dense TSV ("fusion bonded via-in-one") system. Intel once more showing their strong chiplet packing prowess! The claim is that thermals are still much better somehow, in spite of volumetric cell density increasing (from thinner layers). The demo has 8+1 dram+controller layers.

A search for patents by Stephen Morein who is listed as the CTO of SAIMEMORY shows this one, assigned to Intel, and published strangely close to the press release;

https://patents.google.com/patent/US20260040969A1/en

It talks there about 'Z axis memory' rather than angle, and that one is talking about inductive stuff through stacks of vias.

he's also got: https://patentsgazette.uspto.gov/week02/OG/html/1542-2/US125...

He obviously likes thinking about stacks of dies.