| ▲ | lynguist 10 hours ago | |
Indeed!! MIPS - $zero RISC-V - x0 SPARC - %g0 ARM64 - XZR | ||
| ▲ | classichasclass 5 hours ago | parent | next [-] | |
PowerPC: "r0 occasionally" (with certain instructions like addi, though this might be better considered an edge case of encoding) | ||
| ▲ | Findecanor 2 hours ago | parent | prev | next [-] | |
On 64-bit ARM, the same register number is XZR in some instructions and the stack pointer in others. | ||
| ▲ | matja 3 hours ago | parent | prev [-] | |
Alpha: r31, f31 | ||