| ▲ | JSR_FDED 2 days ago |
| What would need to change when the hardware changes? |
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| ▲ | riyaneel 2 days ago | parent [-] |
| Absolutely not, the code following all Hardware principles (Cache coherence/locality, ...) not software abstraction. That not means the code is for a dedicated hardware but designed for modern CPUs. |
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| ▲ | ajb 2 days ago | parent [-] | | Would be more convincing if you enumerated the assumptions. For example, 128b cache lines. Presumably, that is a speed assumption but not a soundness assumption. | | |
| ▲ | riyaneel 2 days ago | parent [-] | | Im currently adding doc, but 128b alignas are for the Adjacent Cache Line prefetcher and avoid to silence the MESI protocol |
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