> ..., fix timing issues.

Which might behave pretty differently on the specific hardware; getting the simulation correct is only a fraction of the path. A lot more is necessary, and usually you spend days (or months depending on the size) with the logic analyzer connected to the board.

> The biggest barrier to FPGAs was always that writing HDL sucked

Are you sure about that? From my experience, that was only 10-30% of the actual work (if your goal is not just to pass the simulator).